1. Field of the Invention
The present invention generally relates to integrated circuit protection devices and, in particular, to a device for protecting an integrated circuit from damage which can be caused by electro-static discharge into an input terminal.
2. Description of the Related Art
A chronic problem associated with semiconductor integrated circuits is the destruction which can be caused by electrostatic discharge (ESD) into any one of the external connector pins. It is commonly known that a 20 to 30 volt discharge into the die interior can result in fatal damage such as junction breakdown, contact breakdown, thermal burnout and, in circuits using gated components, breakdown of the gate oxide layers. Yet in handling a packaged semiconductor chip with exposed terminal pins, simple static discharge from a finger tip can achieve an instantaneous level of tens of thousands of volts.
A common solution to the problem is to convert the high voltage to a current and conduct the current off the die to ground at the terminal pad before incursion into the die. Conventional layouts to create such a shunt path generally use diodes or transistors to act as a clamp device.
One integrated circuit protection device is taught by Avery in U.S. Pat. No. 4,400,711, issued Aug. 23, 1983. Avery teaches an MOS transistor to turn on a silicon controlled rectifier.
In the state of the art, protection devices have been able to dissipate approximately 2000 volts of ESD into a pin. However, with these devices destructive junction breakdown has been found to occur in shallow junction CMOS circuits with an ESD of 500 to 1000 volts. Hence, the available devices are often inadequate, with the result being the destruction of the operability of the integrated circuit.